- Altera DE1-SoC
- 45 min
- Undergraduate, introductory
- English
Digital Logic on the DE1-SoC with VHDL (6/6): FSM capstone -- a vending machine
Students build a VHDL vending-machine FSM, test credit paths on hardware, and try optional change-return checkpoints if time permits.
- Run and explain a non-trivial finite state machine on real hardware.
- Build a vending-machine controller whose state is the accumulated credit.
Includes student questions and response prompts.