- Altera DE1-SoC
- 40 min
- Undergraduate, introductory
- English
Digital Logic on the DE1-SoC with VHDL (4/6): Counters and optional shift registers
Students build a VHDL counter and clock divider, then try optional BCD and shift-register extensions if time permits.
- Explain what a clock divider does and use it to make 50 MHz behavior visible to the eye and camera.
- Build a 4-bit counter and read its value on the LEDs and on a 7-segment display.
Inclui perguntas e campos de resposta para os estudantes.