Teach Remote lab lessons

Educator catalog

LabsLand Teach lessons

Preview public remote-lab activities before signing in to use them with a class.

Reset
More filters

12 lessons

179 public lessons available

Altera DE1-SoC
  • Altera DE1-SoC
  • 50 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (1/6): Your first gates on real hardware

Students write Verilog for basic logic gates, synthesize and upload to the DE1-SoC, and verify truth tables on real switches and LEDs.

  • Explain that Verilog describes hardware, not a program that runs step by step.
  • Use the LabsLand DE1-SoC Verilog workflow: edit, Synthesize, Upload, observe.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 70 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (2/6): Truth tables, SOP/POS, K-maps, and a multiplexer

Students connect truth tables, Boolean forms, Karnaugh maps, and multiplexers, then test minimized combinational logic on DE1-SoC hardware.

  • Derive the sum-of-products (SOP) and product-of-sums (POS) forms from a truth table.
  • Minimize a Boolean function with a Karnaugh map and read off the simplified expression.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 55 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (3/6): Memory — flip-flops and registers

Students build D flip-flop and register circuits in Verilog, test clock and reset behavior, and distinguish combinational logic from stored state.

  • Explain why sequential logic needs memory while combinational logic does not.
  • Describe a D flip-flop as sample-and-hold on the clock edge, with synchronous reset.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 65 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (4/6): Counters and shift registers

Students implement counters and shift registers in Verilog, observe sequential LED patterns, and explain clocked updates on hardware.

  • Explain what a clock divider does and use it to make 50 MHz behavior visible to the eye and camera.
  • Build a 4-bit counter and read its value on the LEDs and on a 7-segment display.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 70 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (5/6): Finite state machines

Students design a finite-state machine for traffic-light-style output, synthesize it, and verify state transitions on the DE1-SoC.

  • Explain what a finite state machine is in terms of states, transitions, and outputs.
  • Distinguish Moore machines (outputs from state) from Mealy machines (outputs from state and inputs).

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 75 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC (6/6): FSM capstone — a vending machine

Students synthesize and upload a Verilog vending-machine FSM to the DE1-SoC, then test switch inputs, KEY reset, LEDR dispense, and HEX credit output.

  • Design and extend a non-trivial finite state machine on real hardware.
  • Build a vending-machine controller whose state is the accumulated credit.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 50 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (1/6): Your first gates on real hardware

Students write VHDL for basic logic gates, synthesize and upload to the DE1-SoC, and verify truth tables on real switches and LEDs.

  • Explain that VHDL describes hardware, not a program that runs step by step.
  • Use the LabsLand DE1-SoC VHDL workflow: edit, Synthesize, Upload, observe.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 45 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (2/6): Truth tables, SOP, K-maps, and optional extensions

Students implement a Boolean function in VHDL as a canonical SOP, minimize it with a K-map, and try optional POS/MUX extensions on the DE1-SoC if time permits.

  • Derive a canonical sum-of-products (SOP) form from a truth table.
  • Minimize a Boolean function with a Karnaugh map and read off the simplified expression.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 55 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (3/6): Memory -- flip-flops and registers

Students use VHDL clocked processes to build a D flip-flop and an 8-bit register, then verify memory behavior on real hardware.

  • Explain why sequential logic needs memory while combinational logic does not.
  • Describe a D flip-flop as sample-and-hold on the clock edge, with synchronous reset.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 40 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (4/6): Counters and optional shift registers

Students build a VHDL counter and clock divider, then try optional BCD and shift-register extensions if time permits.

  • Explain what a clock divider does and use it to make 50 MHz behavior visible to the eye and camera.
  • Build a 4-bit counter and read its value on the LEDs and on a 7-segment display.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 45 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (5/6): Finite state machines

Students build and modify a Moore traffic-light FSM on the DE1-SoC, with an optional Mealy detector extension.

  • Explain what a finite state machine is in terms of states, transitions, and outputs.
  • Explain why the traffic-light controller is a Moore machine, and recognize a Mealy detector as an optional extension.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session
Altera DE1-SoC
  • Altera DE1-SoC
  • 45 min
  • Undergraduate, introductory
  • English

Digital Logic on the DE1-SoC with VHDL (6/6): FSM capstone -- a vending machine

Students build a VHDL vending-machine FSM, test credit paths on hardware, and try optional change-return checkpoints if time permits.

  • Run and explain a non-trivial finite state machine on real hardware.
  • Build a vending-machine controller whose state is the accumulated credit.

Includes student questions and response prompts.

Preview lesson Sign in to create a class session