Digital Logic on the DE1-SoC (1/6): Your first gates on real hardware

Most programming you have seen runs on a processor: instructions execute one after another. In this course you will do something different. You will describe a digital circuit in a language called Verilog, and a real chip will be configured to become that circuit. There is no processor running your lines one by one — your description becomes actual wires and gates that all operate at once.

The chip is an FPGA (Field-Programmable Gate Array): an integrated circuit containing a large grid of logic blocks whose connections can be reconfigured. The board is a Terasic DE1-SoC with an Intel/Altera Cyclone V FPGA — the same board used in many university digital-design courses. You reach a real one through your browser with LabsLand: a server runs Intel Quartus to turn your Verilog into a configuration file, programs the physical board, and streams a live camera so you can see the real LEDs respond.

The board parts you will use in this course:

- SW[9:0] — 10 slide switches you control on screen. A switch up is logic 1.
- KEY[3:0] — 4 pushbuttons. These are active-low: a button reads 0 when pressed and 1 when released.
- CLOCK_50 — a 50 MHz clock signal (used from Lesson 3 on).
- LEDR[9:0] — 10 red LEDs, with LEDR0 at the right end of the row and LEDR9 at the left. These are active-high: an LED lights when you drive it 1.
- HEX0–HEX5 — six 7-segment displays. These are active-low: a segment lights when you drive it 0.

The workflow (the same every lesson): the LabsLand Verilog editor opens with one file, leds_mirror.v, containing a top-level module called leds_mirror. You will replace the contents of that file with the design for the exercise (always keeping the module named leds_mirror), then click Synthesize, wait for it to finish, click Upload to FPGA, and use the on-screen switches while watching the camera. If a guided tour or help overlay covers the editor buttons, close or skip the tour before continuing.

A logic gate takes one or more binary inputs and produces a binary output. Six gates cover almost everything in this course. With inputs A and B:

Truth table for A, B:

- A=0, B=0 -> AND 0, OR 0, NOT A 1, NAND 1, NOR 1, XOR 0
- A=0, B=1 -> AND 0, OR 1, NOT A 1, NAND 1, NOR 0, XOR 1
- A=1, B=0 -> AND 0, OR 1, NOT A 0, NAND 1, NOR 0, XOR 1
- A=1, B=1 -> AND 1, OR 1, NOT A 0, NAND 0, NOR 0, XOR 0

In Verilog these are the bitwise operators & | ~ ^. The design below wires switch SW[0] to A, SW[1] to B, and sends each gate's result to one LED. assign means "this output continuously equals this expression" — exactly what a wire of gates does.

// Lesson 1 — basic gates. Replace ALL contents of leds_mirror.v with this.
module leds_mirror(SW, LEDR);
    input  [9:0] SW;        // SW[0] = A, SW[1] = B (other switches unused)
    output [9:0] LEDR;

    wire A = SW[0];
    wire B = SW[1];

    assign LEDR[0] = A & B;      // AND
    assign LEDR[1] = A | B;      // OR
    assign LEDR[2] = ~A;         // NOT A
    assign LEDR[3] = ~(A & B);   // NAND
    assign LEDR[4] = ~(A | B);   // NOR
    assign LEDR[5] = A ^ B;      // XOR

    assign LEDR[9:6] = 4'b0000;  // unused LEDs held off
endmodule

Before you run it, work out the initial LED pattern yourself. With both switches down, A=0 and B=0 — find that row in the truth table above and decide, for each of the six gates, whether its output is 1. You will check your prediction against the live board in the next step.

Now build the circuit on the real board and check it against the truth table.

Upload your evidence. Capture a camera screenshot with both switches up (SW = 11) — LEDR0 (AND) and LEDR1 (OR) lit, the others off — and attach it in the response box below.