Digital Logic on the DE1-SoC with VHDL (3/6): Memory -- flip-flops and registers

Every design so far has been combinational: the LEDs were a pure function of the switches *right now*. Change a switch and the output changes the instant the signal propagates through the gates. A combinational circuit is stateless — it has no idea what the inputs were a moment ago, and it cannot remember anything.

But most useful systems need memory. A counter has to know its current value to produce the next one. A CPU has to hold operands and results between instructions. A traffic light has to know which colour is showing now to decide what comes next. None of that is possible with gates alone, because gates only ever reflect their present inputs.

Sequential logic is logic that remembers. Its output depends not only on the current inputs but also on stored state — what happened before. The building block that stores one bit of state is the flip-flop, and the timekeeper that tells every flip-flop *when* to update is the clock.

The DE1-SoC provides a free-running 50 MHz clock called CLOCK_50: a square wave that rises and falls 50,000,000 times per second. From this lesson on, your sequential designs must list it as an input. The default blink.vhd template lists only switches, buttons, and LEDs and has no clock, so you will add CLOCK_50 : in std_logic to the entity yourself — forgetting it is the most common error in sequential designs.

A D flip-flop is the simplest memory element. It has a data input D, a clock input, and an output Q. Its entire rule is:

> On every rising edge of the clock, Q captures the value of D and then holds it until the next rising edge.

Between edges, nothing the input does matters — Q is frozen. That is sample-and-hold: the flip-flop samples D at the instant the clock goes from 0 to 1, then holds that sample steady. This is exactly how a circuit gains memory: Q can stay 1 long after D has gone back to 0, because it remembers the sample.

Writing this in VHDL — two new ideas.

First, the clocked process. We describe edge-triggered behaviour with process(CLOCK_50) and if rising_edge(CLOCK_50) then: the signal assignments inside describe what each flip-flop captures on the rising edge, not instructions that run continuously.

Second, signal assignment <=. In VHDL, Q <= SW(0); is a signal assignment. Inside a clocked process it describes a flip-flop update at the clock edge. VHDL variables use := and update immediately inside a process; they can be useful, but they are not the beginner-safe way to describe several registers that should all sample together. Rule of thumb in this course: use signals and <= for stored values such as flip-flops, registers, counters, and FSM state.

Synchronous reset. We also want a way to force Q back to a known value. A synchronous reset is checked *inside* the clocked block, so it only takes effect on a clock edge:

process(CLOCK_50)
begin
    if rising_edge(CLOCK_50) then
        if KEY(0) = '0' then Q <= TODO_RESET_VALUE;
        else                  Q <= TODO_D_INPUT;
        end if;
    end if;
end process;

Because KEY is active-low, the button reads 0 when pressed, so KEY(0) = '0' is true exactly while the reset button is held down.

Build a single D flip-flop on the real board. The wiring is SW(0) = D, KEY(0) = reset (active-low), LEDR(0) = Q, and LEDR(1) = not Q.

Read this before you run it — important. At 50 MHz, Q follows D 50,000,000 times per second, far faster than your eye or the camera can ever see. So even though this circuit *does* store D, you cannot *watch* it store: flip SW(0) and LEDR(0) appears to follow instantly. That is why this exercise really demonstrates reset, not storage. The behaviour you will actually observe:

- With SW(0) up (D=1), LEDR(0) is on (and LEDR(1), showing not Q, is off).
- Hold KEY(0) (pressed reads 0, so reset is active): LEDR(0) goes off even though SW(0) is still up. The reset wins over the data.
- Release KEY(0): LEDR(0) follows SW(0) again.

You will *see* memory in the next exercise (2-B). For now, focus on the reset overriding the data input.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 3 - Exercise 2-A: D flip-flop.
-- SW(0)=D, KEY(0)=reset (active-low reset), LEDR(0)=Q, LEDR(1)=not Q.
library ieee;
use ieee.std_logic_1164.all;

entity blink is
    port (
        CLOCK_50 : in  std_logic;
        KEY      : in  std_logic_vector(3 downto 0);
        SW       : in  std_logic_vector(9 downto 0);
        LEDR     : out std_logic_vector(9 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal Q : std_logic := '0';
begin
    process(CLOCK_50)
    begin
        if rising_edge(CLOCK_50) then
            if KEY(0) = '0' then Q <= TODO_RESET_VALUE;
            else                  Q <= TODO_D_INPUT;
            end if;
        end if;
    end process;

    LEDR(0) <= TODO_Q_OUTPUT;
    LEDR(1) <= TODO_NOT_Q_OUTPUT;
    LEDR(9 downto 2) <= (others => '0');
end architecture rtl;

A register is just N D flip-flops side by side, all sharing the same clock and the same reset. An 8-bit register stores 8 bits. A parallel load copies all 8 input bits into the register at once on a clock edge — every flip-flop captures its own data bit simultaneously.

The trick that makes memory visible here is the load control. Instead of capturing the data on *every* edge (as the bare flip-flop did), this register only captures when you tell it to. So you can change the switches all you like and the stored value stays put — until you load. The wiring is SW(7 downto 0) = data, KEY(0) = reset (active-low), KEY(1) = load (active-low).

Because KEY is active-low, you press and release KEY(1) to load: pressing makes KEY(1) read 0, and the code tests KEY(1) = '0' to detect that. Note KEY(1) is *sampled on the clock*, not a hardware-debounced clock signal — the design simply checks the button's level at each rising edge, which is fine for this exercise.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 3 - Exercise 2-B: 8-bit parallel-load register.
-- SW(7 downto 0)=data, KEY(0)=reset, KEY(1)=load. KEY inputs are active-low.
library ieee;
use ieee.std_logic_1164.all;

entity blink is
    port (
        CLOCK_50 : in  std_logic;
        KEY      : in  std_logic_vector(3 downto 0);
        SW       : in  std_logic_vector(9 downto 0);
        LEDR     : out std_logic_vector(9 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal Q : std_logic_vector(7 downto 0) := (others => '0');
begin
    process(CLOCK_50)
    begin
        if rising_edge(CLOCK_50) then
            if KEY(0) = '0' then
                Q <= TODO_RESET_VECTOR;
            elsif KEY(1) = '0' then
                Q <= TODO_LOAD_VALUE;
            end if; -- otherwise Q holds its previous value
        end if;
    end process;

    LEDR(7 downto 0) <= TODO_REGISTER_OUTPUT;
    LEDR(9 downto 8) <= (others => '0');
end architecture rtl;

Upload your evidence. Capture a camera screenshot that proves the register is *holding*: LEDR(7 downto 0) reads 10101010 (the previously loaded value) while the on-screen switches SW(7 downto 0) are set to a different pattern such as 01010101 and you have not pressed KEY(1). Show both the held LEDs and the different switch positions, and attach it below.

You built the two foundations of all memory in digital systems: the D flip-flop (one bit, sample-and-hold on the clock edge) and the register (many flip-flops loaded in parallel, holding their value until told otherwise). You used a VHDL clocked process with rising_edge(CLOCK_50) and signal assignments (<=), and you saw an active-low KEY act as a control input.

A note carried forward — two styles of reset. Both designs in this lesson used a synchronous reset: the reset was checked inside the clocked process, so it only took effect on a rising clock edge. That is clean and predictable for these simple storage elements. Starting with the slow-clock designs in Lesson 4, and continuing in the finite-state-machine lessons (5 and 6), you will also see active-low asynchronous reset written as a process(..., KEY) with if KEY(0) = '0' then ... before the clock-edge branch; that reset forces the circuit to a safe state immediately, without waiting for the slow clock.