Digital Logic on the DE1-SoC (2/6): Truth tables, SOP/POS, K-maps, and a multiplexer

In Lesson 1 you wired single gates to switches. Real designs start one level up: you decide what a circuit should do — usually as a truth table — and then find a gate network that produces it. This lesson works one function from both directions and then makes it smaller.

The function for the first two exercises is F(C,B,A), a function of three inputs. You will wire SW[0]=A, SW[1]=B, SW[2]=C, and show the result on LEDR[0]. Here is its truth table. The rows are listed in binary counting order C B A from 000 to 111:

Truth table for F(C,B,A), in binary counting order:

- Row 0: C B A = 0 0 0 -> F=0
- Row 1: C B A = 0 0 1 -> F=1
- Row 2: C B A = 0 1 0 -> F=0
- Row 3: C B A = 0 1 1 -> F=1
- Row 4: C B A = 1 0 0 -> F=1
- Row 5: C B A = 1 0 1 -> F=0
- Row 6: C B A = 1 1 0 -> F=1
- Row 7: C B A = 1 1 1 -> F=0

F is 1 on four of the eight rows and 0 on the other four — read them off the table yourself before you answer below. This split drives the whole lesson: the F=1 rows give you the sum of products, and the F=0 rows give you the product of sums. Keep this table in front of you for both exercises — everything below refers back to it.

Recall the board conventions you used in Lesson 1: a switch up is logic 1, and LEDR is active-high, so the LED lights when the output is 1. These exercises are purely combinational — the output depends only on the current switch positions, so there is no clock to declare.

Minterm. A *minterm* is a single AND (product) term built from all the inputs — each input appears once, plain or negated — that is 1 for exactly one row of the truth table. For three inputs there are eight minterms, one per row. Row 1 is C=0, B=0, A=1, so its minterm is (~C & ~B & A): this product is 1 only when C=0, B=0, and A=1, and 0 everywhere else.

Canonical sum of products (SOP). To build F, OR together the minterm of every row where F=1. Because each minterm is 1 for exactly its own row, the OR is 1 on precisely the F=1 rows and 0 elsewhere. Use the truth table above to write the four minterms for F yourself. Do not skip the full form: you will test it on the board before you test the reduced form.

Minimizing with a Karnaugh map. A *K-map* is the truth table redrawn so that physically adjacent cells differ in exactly one input. When two adjacent 1s sit next to each other, the variable that *changes* between them does not matter for that pair and can be dropped, leaving a smaller term. The diagram below marks the four 1 cells and shows two possible groups. Your job is to read each group: identify which input stays fixed, which input changes, and what product term remains.

Now put the function on the real board. You will run the canonical SOP first, verify all eight rows, then edit the same starter to test the minimal expression you derived from the K-map.

The module below is intentionally incomplete. Replace the TODO_CANONICAL_SOP_EXPRESSION placeholder with your full SOP. After you verify it on the board, replace that same line with your minimized expression and synthesize again.

// Lesson 2 - Exercise 1-B: Sum of Products (SOP) starter
// F(C,B,A): use the truth-table rows where F=1. SW[0]=A, SW[1]=B, SW[2]=C.
// Fill the canonical SOP first. Then replace it with your K-map minimized expression.
module leds_mirror(SW, LEDR);
    input  [9:0] SW;
    output [9:0] LEDR;

    wire A = SW[0];
    wire B = SW[1];
    wire C = SW[2];

    // Pass 1: canonical SOP. Write one product term for each F=1 row.
    assign LEDR[0] = TODO_CANONICAL_SOP_EXPRESSION;

    // Pass 2: after you verify the canonical form, replace the line above with
    // your minimized K-map expression and synthesize again.

    assign LEDR[9:1] = 9'b0;
endmodule

Upload your evidence. Capture a camera screenshot of your minimized expression running on any row where your truth table predicts F=1, and attach it below. In the caption or text field, state the C B A row you chose.

> Optional bonus (no upload required). Quartus reports how many logic elements a design uses. If your lab surfaces that resource report, synthesize your canonical SOP and your minimized expression and compare their logic-element counts. Treat this as exploration only; the in-IDE resource report is not guaranteed on every lab session, so it is not part of the required evidence.

The SOP built F from its 1 rows. The product of sums (POS) builds the same F from its 0 rows instead.

Maxterm. A *maxterm* is a single OR (sum) term using all the inputs — each plain or negated — that is 0 for exactly one row. It is the mirror image of a minterm. For row 0 (C=0, B=0, A=0) the maxterm is (A | B | C): this OR is 0 only when A, B, and C are all 0, and 1 on every other row.

Canonical product of sums. AND together the maxterm of every row where F=0. Each maxterm forces the output to 0 on its own row and leaves it 1 elsewhere, so the AND of all of them is 0 on exactly the F=0 rows. Read the F=0 rows from the truth table and write the four maxterms yourself.

// Lesson 2 - Exercise 1-C: Product of Sums (POS) starter
// Same F(C,B,A). Use the truth-table rows where F=0 to write the maxterms.
module leds_mirror(SW, LEDR);
    input  [9:0] SW;
    output [9:0] LEDR;

    wire A = SW[0];
    wire B = SW[1];
    wire C = SW[2];

    // Canonical POS: one sum term for each F=0 row, ANDed together.
    assign LEDR[0] = TODO_CANONICAL_POS_EXPRESSION;

    assign LEDR[9:1] = 9'b0;
endmodule

A multiplexer (MUX) is a selector: it routes one of several data inputs to a single output, chosen by a set of select lines. A 4-to-1 MUX has four data inputs and needs two select lines (because two bits choose among 2^2 = 4 inputs). It behaves like a rotary switch: the select value picks which data line is connected to the output.

The pin assignment for this exercise — stated explicitly so the bit order is unambiguous:

- Data inputs: SW[3]=D3, SW[2]=D2, SW[1]=D1, SW[0]=D0
- Select lines: SW[5]=S1, SW[4]=S0
- Output: LEDR[0] = Y

The select value {S1, S0} chooses the data line: 00 → D0, 01 → D1, 10 → D2, 11 → D3. The module uses a case statement inside always @(*). The default branch is not decorative — in a combinational always block, if some input combination left Y unassigned, the synthesizer would infer a latch to "remember" the old value, turning your intended pure-combinational logic into accidental memory. Assigning Y in every branch (here via default) guarantees Y always has a defined value and no latch is created.

// Lesson 2 - Exercise 1-D: 4-to-1 multiplexer starter
// Data inputs: SW[3]=D3, SW[2]=D2, SW[1]=D1, SW[0]=D0
// Select lines: SW[5]=S1, SW[4]=S0. Output: LEDR[0]=Y.
module leds_mirror(SW, LEDR);
    input  [9:0] SW;
    output [9:0] LEDR;

    wire D0 = SW[0], D1 = SW[1], D2 = SW[2], D3 = SW[3];
    wire S0 = SW[4], S1 = SW[5];

    reg Y;
    always @(*) begin
        case ({S1, S0})
            2'b00:   Y = TODO_SELECTED_INPUT_00;
            2'b01:   Y = TODO_SELECTED_INPUT_01;
            2'b10:   Y = TODO_SELECTED_INPUT_10;
            2'b11:   Y = TODO_SELECTED_INPUT_11;
            default: Y = 1'b0;   // default avoids an inferred latch
        endcase
    end

    assign LEDR[0]   = Y;
    assign LEDR[9:1] = 9'b0;
endmodule

Upload your evidence. Capture a camera screenshot of the multiplexer with data SW[3:0] = 1010 and select S1:S0 = 01 (SW[4] up, SW[5] down) — this selects D1 = 1, so LEDR[0] is lit — and attach it below.

This exercise is optional. If you have time, it is a satisfying jump from a single LED to formatted output on the seven-segment displays.

A seven-segment display has seven bars — labelled a through g — that light in combinations to draw a digit. On the DE1-SoC each HEX display is active-low and the bit order is {g, f, e, d, c, b, a}: a segment lights when you drive its bit to 0. So the pattern for the digit 0 (segments a,b,c,d,e,f on, g off) is 7'b1000000 — six 0s for the lit segments and a 1 for the unlit g.

The design below reads SW[3:0] as a value 0..15, shows the ones digit on HEX0 and the tens digit (0 or 1) on HEX1. Note one thing the default project does not give you for free: to drive HEX1 you must add output [6:0] HEX1 to the module's port list — the starter leds_mirror exposes only HEX0. The module below already declares both HEX0 and HEX1, so this is the example that makes the extra port concrete.

// Lesson 2 - Exercise 1-E (optional): two-digit decimal decoder starter
// Complete the active-low digit patterns and the tens/ones equations.
module leds_mirror(SW, HEX0, HEX1);
    input  [9:0] SW;        // SW[3:0] = value 0..15
    output [6:0] HEX0;      // ones digit
    output [6:0] HEX1;      // tens digit (0 or 1)

    wire [4:0] v = {1'b0, SW[3:0]};

    function [6:0] seg;
        input [3:0] d;
        case (d)
            4'd0: seg = 7'b1000000;
            4'd1: seg = TODO_SEGMENT_PATTERN_1;
            4'd2: seg = TODO_SEGMENT_PATTERN_2;
            4'd3: seg = TODO_SEGMENT_PATTERN_3;
            4'd4: seg = TODO_SEGMENT_PATTERN_4;
            4'd5: seg = TODO_SEGMENT_PATTERN_5;
            4'd6: seg = TODO_SEGMENT_PATTERN_6;
            4'd7: seg = TODO_SEGMENT_PATTERN_7;
            4'd8: seg = TODO_SEGMENT_PATTERN_8;
            4'd9: seg = TODO_SEGMENT_PATTERN_9;
            default: seg = 7'b1111111;
        endcase
    endfunction

    wire [3:0] tens = TODO_TENS_DIGIT;
    wire [3:0] ones = TODO_ONES_DIGIT;

    assign HEX0 = seg(ones);
    assign HEX1 = seg(tens);
endmodule