Digital Logic on the DE1-SoC with VHDL (2/6): Truth tables, SOP, K-maps, and optional extensions

In Lesson 1 you wired single gates to switches. Real designs start one level up: you decide what a circuit should do — usually as a truth table — and then find a gate network that produces it. This lesson works one function from both directions and then makes it smaller.

The function for the first two exercises is F(C,B,A), a function of three inputs. You will wire SW(0)=A, SW(1)=B, SW(2)=C, and show the result on LEDR(0). Here is its truth table. The rows are listed in binary counting order C B A from 000 to 111:

Truth table for F(C,B,A), in binary counting order:

- Row 0: C B A = 0 0 0 -> F=0
- Row 1: C B A = 0 0 1 -> F=1
- Row 2: C B A = 0 1 0 -> F=0
- Row 3: C B A = 0 1 1 -> F=1
- Row 4: C B A = 1 0 0 -> F=1
- Row 5: C B A = 1 0 1 -> F=0
- Row 6: C B A = 1 1 0 -> F=1
- Row 7: C B A = 1 1 1 -> F=0

F is 1 on four of the eight rows and 0 on the other four — read them off the table yourself before you answer below. This split drives the whole lesson: the F=1 rows give you the sum of products, and the F=0 rows give you the product of sums. Keep this table in front of you for both exercises — everything below refers back to it.

Recall the board conventions you used in Lesson 1: a switch up is logic 1, and LEDR is active-high, so the LED lights when the output is 1. These exercises are purely combinational — the output depends only on the current switch positions, so there is no clock to declare.

Minterm. A *minterm* is a single AND (product) term built from all the inputs — each input appears once, plain or negated — that is 1 for exactly one row of the truth table. For three inputs there are eight minterms, one per row. Row 1 is C=0, B=0, A=1, so its minterm is (not C and not B and A): this product is 1 only when C=0, B=0, and A=1, and 0 everywhere else.

Canonical sum of products (SOP). To build F, OR together the minterm of every row where F=1. Because each minterm is 1 for exactly its own row, the OR is 1 on precisely the F=1 rows and 0 elsewhere — which is exactly F. The four F=1 rows (1, 3, 4, 6) give:

- Row 1 C=0,B=0,A=1 → (not C and not B and A)
- Row 3 C=0,B=1,A=1 → (not C and B and A)
- Row 4 C=1,B=0,A=0 → (C and not B and not A)
- Row 6 C=1,B=1,A=0 → (C and B and not A)

So the canonical SOP is F = (not C and not B and A) or (not C and B and A) or (C and not B and not A) or (C and B and not A). That is correct but wasteful: four 3-input AND terms feeding a 4-input OR.

Minimizing with a Karnaugh map. A *K-map* is the truth table redrawn so that physically adjacent cells differ in exactly one input. When two adjacent 1s sit next to each other, the variable that *changes* between them does not matter for that pair and can be dropped.

Group the four F=1 minterms into two pairs:

- Group minterms 1 and 3. Row 1 is C=0, B=0, A=1; row 3 is C=0, B=1, A=1. Note which variables stay the same and which one changes. The changing variable is eliminated.
- Group minterms 4 and 6. Row 4 is C=1, B=0, A=0; row 6 is C=1, B=1, A=0. Make the same comparison. This group wraps around the edge of the map because columns 00 and 10 are also adjacent in Gray-code order.

Write one reduced term for each group and combine the two terms with or. If you recognize a known gate, you may write the equivalent form; otherwise keep the two-product-term expression. Also check which input disappears from both groups and what that says about how F depends on its inputs.

Now put the function on the real board. You will run the canonical SOP first, verify all eight rows, then switch to your minimized expression and confirm you get the identical outputs.

The starter entity below deliberately leaves the expression for LEDR(0) as TODOs. For the first pass, complete the active canonical SOP assignment from the four minterms. For the second pass, replace it with the minimized expression from the K-map, then synthesize again and compare.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 2 - Exercise 1-B: Sum of Products.
-- F(C,B,A): minterms 1,3,4,6. SW(0)=A, SW(1)=B, SW(2)=C. Output on LEDR(0).
library ieee;
use ieee.std_logic_1164.all;

entity blink is
    port (
        SW   : in  std_logic_vector(9 downto 0);
        LEDR : out std_logic_vector(9 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal A, B, C : std_logic;
begin
    A <= SW(0);
    B <= SW(1);
    C <= SW(2);

    -- First pass: complete the canonical SOP expression from the four minterms.
    LEDR(0) <= TODO_CANONICAL_SOP;

    -- Second pass: replace the line above with the minimized expression from the K-map.
    -- LEDR(0) <= TODO_MINIMIZED_EXPRESSION;
    LEDR(9 downto 1) <= (others => '0');
end architecture rtl;

Upload your evidence. Capture a camera screenshot of your minimized expression running with the switches set to a row where F = 1 (for example C B A = 100: SW(2) up, SW(1) and SW(0) down, so LEDR(0) is lit), and attach it below.

> Optional bonus (no upload required). Quartus reports how many logic elements a design uses. If your lab surfaces that resource report, synthesize the four-term canonical SOP and the one-operator your minimized expression and compare their logic-element counts — the minimal form should use fewer. Treat this as exploration only; the in-IDE resource report is not guaranteed on every lab session, so it is not part of the required evidence.

Optional extension if your teacher has time: the SOP built F from its 1 rows. The product of sums (POS) builds the same F from its 0 rows instead.

Maxterm. A *maxterm* is a single OR (sum) term using all the inputs — each plain or negated — that is 0 for exactly one row. It is the mirror image of a minterm. For row 0 (C=0, B=0, A=0) the maxterm is (A or B or C): this OR is 0 only when A, B, and C are all 0, and 1 on every other row.

Canonical product of sums. AND together the maxterm of every row where F=0. Each maxterm forces the output to 0 on its own row and leaves it 1 elsewhere, so the AND of all of them is 0 on exactly the F=0 rows — again exactly F. The four F=0 rows are 0, 2, 5, 7:

- Row 0 C=0,B=0,A=0 → (A or B or C)
- Row 2 C=0,B=1,A=0 → (A or not B or C)
- Row 5 C=1,B=0,A=1 → (not A or B or not C)
- Row 7 C=1,B=1,A=1 → (not A or not B or not C)

In each maxterm, a variable appears *negated* when it is 1 in that F=0 row (so the term goes to 0 there). The entity below implements this canonical POS directly. It describes the very same function, so its eight outputs must match what you already recorded: rows 0..7 give 0, 1, 0, 1, 1, 0, 1, 0.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 2 - Exercise 1-C: Product of Sums (POS).
-- Same F(C,B,A). Maxterms (F=0 rows): 0, 2, 5, 7. SW(0)=A, SW(1)=B, SW(2)=C.
library ieee;
use ieee.std_logic_1164.all;

entity blink is
    port (
        SW   : in  std_logic_vector(9 downto 0);
        LEDR : out std_logic_vector(9 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal A, B, C : std_logic;
begin
    A <= SW(0);
    B <= SW(1);
    C <= SW(2);

    LEDR(0) <= TODO_POS_EXPRESSION; -- TODO: product of maxterm sums
    LEDR(9 downto 1) <= (others => '0');
end architecture rtl;

Optional extension if your teacher wants a selector example: a multiplexer (MUX) routes one of several data inputs to a single output, chosen by a set of select lines. A 4-to-1 MUX has four data inputs and needs two select lines (because two bits choose among 2^2 = 4 inputs). It behaves like a rotary switch: the select value picks which data line is connected to the output.

The pin mapping for this exercise — stated explicitly so the bit order is unambiguous:

- Data inputs: SW(3)=D3, SW(2)=D2, SW(1)=D1, SW(0)=D0
- Select lines: SW(5)=S1, SW(4)=S0
- Output: LEDR(0) = Y

The select value S1 & S0 chooses the data line: 00 -> D0, 01 -> D1, 10 -> D2, 11 -> D3. The entity uses VHDL with sel select, ending with when others. That final branch is not decorative: in combinational VHDL, every output must receive a value for every possible input. If some path left Y unassigned, the synthesizer would infer a latch to remember the old value, turning pure combinational logic into accidental memory.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 2 - Exercise 1-D: 4-to-1 multiplexer using selected signal assignment.
-- Data: SW(3)=D3, SW(2)=D2, SW(1)=D1, SW(0)=D0. Select: SW(5)=S1, SW(4)=S0.
library ieee;
use ieee.std_logic_1164.all;

entity blink is
    port (
        SW   : in  std_logic_vector(9 downto 0);
        LEDR : out std_logic_vector(9 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal D0, D1, D2, D3 : std_logic;
    signal S0, S1, Y      : std_logic;
    signal sel            : std_logic_vector(1 downto 0);
begin
    D0 <= SW(0); D1 <= SW(1); D2 <= SW(2); D3 <= SW(3);
    S0 <= SW(4); S1 <= SW(5);
    sel <= S1 & S0;

    with sel select
        Y <= TODO_FOR_00 when "00",
             TODO_FOR_01 when "01",
             TODO_FOR_10 when "10",
             TODO_FOR_11 when "11",
             '0' when others;

    LEDR(0) <= Y;
    LEDR(9 downto 1) <= (others => '0');
end architecture rtl;

Upload your evidence. Capture one camera screenshot from your multiplexer test. In the table above, mark the row that matches the screenshot so your teacher can compare the predicted and observed Y.

This exercise is optional. If you have time, it is a satisfying jump from a single LED to formatted output on the seven-segment displays.

A seven-segment display has seven bars — labelled a through g — that light in combinations to draw a digit. On the DE1-SoC each HEX display is active-low and the bit order is {g, f, e, d, c, b, a}: a segment lights when you drive its bit to 0. So the pattern for the digit 0 (segments a,b,c,d,e,f on, g off) is "1000000" — six 0s for the lit segments and a 1 for the unlit g.

The design below reads SW(3 downto 0) as a value 0..15, shows the ones digit on HEX0 and the tens digit (0 or 1) on HEX1. Note one thing the default project does not give you for free: to drive HEX1 you must add HEX1 : out std_logic_vector(6 downto 0) to the entity's port list — the starter blink exposes only HEX0. The entity below already declares both HEX0 and HEX1, so this is the example that makes the extra port concrete.

-- Student starter: fill the TODO lines before synthesizing.
-- Lesson 2 - Exercise 1-E (optional): two-digit decimal decoder.
-- SW(3 downto 0) selects 0..15. HEX0 shows ones; HEX1 shows tens.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity blink is
    port (
        SW   : in  std_logic_vector(9 downto 0);
        HEX0 : out std_logic_vector(6 downto 0);
        HEX1 : out std_logic_vector(6 downto 0)
    );
end entity blink;

architecture rtl of blink is
    signal v    : unsigned(4 downto 0);
    signal tens : unsigned(3 downto 0);
    signal ones : unsigned(3 downto 0);

    function seg(d : unsigned(3 downto 0)) return std_logic_vector is
    begin
        case d is
            when "0000" => return "1000000"; -- 0
            when "0001" => return TODO_SEG_1;
            when "0010" => return TODO_SEG_2;
            when "0011" => return TODO_SEG_3;
            when others => return "1111111";
        end case;
    end function;
begin
    v <= resize(unsigned(SW(3 downto 0)), 5);
    tens <= TODO_TENS;
    ones <= TODO_ONES;

    HEX0 <= seg(ones);
    HEX1 <= seg(tens);
end architecture rtl;