Digital Logic on the DE1-SoC (3/6): Memory — flip-flops and registers

Every design so far has been combinational: the LEDs were a pure function of the switches *right now*. Change a switch and the output changes the instant the signal propagates through the gates. A combinational circuit is stateless — it has no idea what the inputs were a moment ago, and it cannot remember anything.

But most useful systems need memory. A counter has to know its current value to produce the next one. A CPU has to hold operands and results between instructions. A traffic light has to know which colour is showing now to decide what comes next. None of that is possible with gates alone, because gates only ever reflect their present inputs.

Sequential logic is logic that remembers. Its output depends not only on the current inputs but also on stored state — what happened before. The building block that stores one bit of state is the flip-flop, and the timekeeper that tells every flip-flop *when* to update is the clock.

The DE1-SoC provides a free-running 50 MHz clock called CLOCK_50: a square wave that rises and falls 50,000,000 times per second. From this lesson on, your sequential designs must list it as an input. The default leds_mirror.v template lists only switches, buttons, and LEDs and has no clock, so you will add input CLOCK_50; to the module yourself — forgetting it is the most common error in sequential designs.

A D flip-flop is the simplest memory element. It has a data input D, a clock input, and an output Q. Its entire rule is:

> On every rising edge of the clock, Q captures the value of D and then holds it until the next rising edge.

Between edges, nothing the input does matters — Q is frozen. That is sample-and-hold: the flip-flop samples D at the instant the clock goes from 0 to 1, then holds that sample steady. This is exactly how a circuit gains memory: Q can stay 1 long after D has gone back to 0, because it remembers the sample.

Writing this in Verilog — two new ideas.

First, the clocked block. We describe edge-triggered behaviour with always @(posedge CLOCK_50): the statements inside run once at each rising edge, not continuously. A signal assigned inside such a block must be declared reg (it holds a value between edges).

Second, non-blocking assignment <=. Inside a clocked block, always use <=, not =. The <= operator means "schedule all the right-hand sides to be sampled now, then update the left-hand sides together at the edge" — which is exactly how real flip-flops behave (they all sample at once). Using = (blocking) inside a clocked block is a classic Verilog bug: the assignments take effect in sequence within the edge, so one flip-flop can see another's *new* value instead of its old one, producing hardware that does not match your intent. Rule of thumb: <= in clocked blocks, = only in combinational assign/always @(*).

Synchronous reset. We also want a way to force Q back to a known value. A synchronous reset is checked *inside* the clocked block, so it only takes effect on a clock edge:

always @(posedge CLOCK_50) begin
    if (!KEY[0]) Q <= 1'b0;   // synchronous reset, evaluated at the edge
    else         Q <= SW[0];  // otherwise capture D
end

Because KEY is active-low, the button reads 0 when pressed, so !KEY[0] is true exactly while the reset button is held down.

Build a single D flip-flop on the real board. The wiring is SW[0] = D, KEY[0] = reset (active-low), LEDR[0] = Q, and LEDR[1] = ~Q.

Read this before you run it — important. At 50 MHz, Q follows D 50,000,000 times per second, far faster than your eye or the camera can ever see. So even though this circuit *does* store D, you cannot *watch* it store: flip SW[0] and LEDR[0] appears to follow instantly. That is why this exercise really demonstrates reset, not storage. The behaviour you will actually observe:

- With SW[0] up (D=1), LEDR[0] is on (and LEDR[1], showing ~Q, is off).
- Hold KEY[0] (pressed reads 0, so reset is active): LEDR[0] goes off even though SW[0] is still up. The reset wins over the data.
- Release KEY[0]: LEDR[0] follows SW[0] again.

You will *see* memory in the next exercise (2-B). For now, focus on the reset overriding the data input.

// Lesson 3 - Exercise 2-A: D flip-flop
// SW[0]=D, KEY[0]=reset (active-low), LEDR[0]=Q, LEDR[1]=~Q.
// Note: at 50 MHz, Q follows D faster than the eye/camera can see, so the
// clearly visible behavior here is RESET. Storage is demonstrated in 2-B.
module leds_mirror(CLOCK_50, KEY, SW, LEDR);
    input        CLOCK_50;
    input  [3:0] KEY;       // KEY[0] = reset_n (active-low)
    input  [9:0] SW;        // SW[0]  = D
    output [9:0] LEDR;

    reg Q;
    always @(posedge CLOCK_50) begin
        if (!KEY[0]) Q <= 1'b0;    // synchronous reset: takes effect on the clock edge
        else         Q <= SW[0];   // capture D on every rising clock edge
    end

    assign LEDR[0]   = Q;
    assign LEDR[1]   = ~Q;
    assign LEDR[9:2] = 8'b0;
endmodule

A register is just N D flip-flops side by side, all sharing the same clock and the same reset. An 8-bit register stores 8 bits. A parallel load copies all 8 input bits into the register at once on a clock edge — every flip-flop captures its own data bit simultaneously.

The trick that makes memory visible here is the load control. Instead of capturing the data on *every* edge (as the bare flip-flop did), this register only captures when you tell it to. So you can change the switches all you like and the stored value stays put — until you load. The wiring is SW[7:0] = data, KEY[0] = reset (active-low), KEY[1] = load (active-low).

Because KEY is active-low, you press and release KEY[1] to load: pressing makes KEY[1] read 0, and the code tests !KEY[1] to detect that. Note KEY[1] is *sampled on the clock*, not a hardware-debounced clock signal — the design simply checks the button's level at each rising edge, which is fine for this exercise.

// Lesson 3 - Exercise 2-B: 8-bit parallel-load register
// SW[7:0]=data, KEY[0]=reset (active-low), KEY[1]=load (active-low). LEDR[7:0]=stored value.
// Because KEY is active-low, "press and release KEY[1]" loads the switches; the code tests !KEY[1].
module leds_mirror(CLOCK_50, KEY, SW, LEDR);
    input        CLOCK_50;
    input  [3:0] KEY;       // KEY[0]=reset_n, KEY[1]=load_n
    input  [9:0] SW;        // SW[7:0] = data to load
    output [9:0] LEDR;

    reg [7:0] Q;
    always @(posedge CLOCK_50) begin
        if (!KEY[0])      Q <= 8'h00;     // reset overrides load
        else if (!KEY[1]) Q <= SW[7:0];   // parallel load while KEY[1] is held
        // else: hold (Q keeps its value even when the switches change)
    end

    assign LEDR[7:0] = Q;
    assign LEDR[9:8] = 2'b0;
endmodule

Upload your evidence. Capture a camera screenshot that proves the register is *holding*: LEDR[7:0] reads 10101010 (the previously loaded value) while the on-screen switches SW[7:0] are set to a different pattern such as 01010101 and you have not pressed KEY[1]. Show both the held LEDs and the different switch positions, and attach it below.

You built the two foundations of all memory in digital systems: the D flip-flop (one bit, sample-and-hold on the clock edge) and the register (many flip-flops loaded in parallel, holding their value until told otherwise). You used always @(posedge CLOCK_50) with non-blocking <=, and you saw an active-low KEY act as a control input.

A note carried forward — two styles of reset. Both designs in this lesson used a synchronous reset: the reset was checked *inside* the clocked block, so it only took effect on a rising clock edge. That is clean and predictable, and it is what you will keep using for the simple storage elements in this lesson and the next. However, the finite-state-machine lessons (5 and 6) will switch to an active-low asynchronous reset (written as always @(posedge CLOCK_50 or negedge KEY[0])), which forces the circuit to a safe state immediately, without waiting for a clock edge — useful for getting a stuck state machine back under control on the board. The detailed difference, and why FSMs prefer the asynchronous style, will be explained there. For now, just know the two styles exist and that this lesson deliberately used the synchronous one.