Nios V on DE1-SoC (4/5): HEX display and timer

In the previous lessons, you used memory-mapped I/O for simple controls: browser NSW inputs, JP1 GPIO data, and LEDR outputs. This lesson keeps the same idea but uses two richer peripherals already built into the fixed FPGA system.

A peripheral is a hardware block that the Nios V processor controls by reading or writing a specific address. You are not changing the FPGA design in this lesson. You are replacing main.c with small C examples, building an ELF, uploading it, and checking whether the board behavior matches the register-level explanation.

The two required examples are:

- hex_counter, which writes encoded patterns to HEX0.
- timer_blink, which configures the interval timer and toggles LEDR0.

For a complete register map, use the FPGAcademy DE1-SoC Computer with Nios V user manual. This activity gives you the subset you need: HEX3_HEX0 at 0xFF200020 and the interval timer at 0xFF202000.

The browser shows Nios-specific logical button controls labelled NB0..NB3. These are validated JP1/GPIO inputs, not the FPGAcademy KEY register at 0xFF200050.

For the required work in this lesson, use the HEX and timer examples below. The optional button section is self-contained if it is assigned: use NB0..NB3 as logical JP1 inputs and avoid KEY0..KEY3 wording.

The HEX displays are seven-segment displays. A digit is not written as the number 3; it is written as a bit pattern that turns individual segments on or off.

The hex_counter example writes segment patterns to HEX3_HEX0 at 0xFF200020.

Each byte in HEX3_HEX0 controls one display. In this starter, only the low byte is used, so only HEX0 changes. A value such as 0x3F is not the number zero in the usual sense; it is the segment pattern that lights the segments needed to draw 0.

Examples:

- Digit 0 uses pattern 0x3F.
- Digit 1 uses pattern 0x06.
- Digit A uses pattern 0x77.

Use this source for hex_counter:

Select the full code block before copying it into main.c; the whole starter
source should be replaced.

/* DE1-SoC Computer with Nios V -- memory-mapped I/O */
volatile int *HEX3_HEX0 = (int *) 0xFF200020;  /* 7-seg HEX3..HEX0 */

static const unsigned char HEX_CODE[16] = {
    0x3F, 0x06, 0x5B, 0x4F,
    0x66, 0x6D, 0x7D, 0x07,
    0x7F, 0x67, 0x77, 0x7C,
    0x39, 0x5E, 0x79, 0x71
};

static void delay(void)
{
    volatile int i;
    for (i = 0; i < 2000000; i++) {
    }
}

int main(void)
{
    int count = 0;

    while (1) {
        *HEX3_HEX0 = HEX_CODE[count & 0xF];
        count++;
        delay();
    }
    return 0;
}

Use the table to record what you saw after uploading hex_counter. The expected behavior is already filled in. Add two different HEX0 digits or segment patterns you saw, then enter pass, fail, or uncertain in the result column.

The timer_blink example programs the FPGA interval timer at base address 0xFF202000. It sets a period, starts the timer, polls the timeout bit, clears it, and toggles LEDR0.

The timer clock is 100 MHz, so 50,000,000 ticks is about half a second. The 32-bit period is split into two 16-bit registers because the timer interface stores the low and high halves separately.

Timer registers used here:

- STATUS at offset +0x0: bit 0, TO, becomes 1 when the period expires.
- CONTROL at offset +0x4: STOP, START, and CONT control whether the timer runs continuously.
- PERIOD_LO at offset +0x8: low 16 bits of the period.
- PERIOD_HI at offset +0xC: high 16 bits of the period.

Use this source for timer_blink:

Select the full code block before copying it into main.c; the whole previous
source should be replaced.

/* DE1-SoC Computer with Nios V -- memory-mapped I/O */
volatile int *LEDS = (int *) 0xFF200000;  /* red LEDs */

#define TIMER_BASE      0xFF202000
#define TIMER_STATUS    (*(volatile short *)(TIMER_BASE + 0x0))
#define TIMER_CONTROL   (*(volatile short *)(TIMER_BASE + 0x4))
#define TIMER_PERIOD_LO (*(volatile short *)(TIMER_BASE + 0x8))
#define TIMER_PERIOD_HI (*(volatile short *)(TIMER_BASE + 0xC))

#define TIMER_TO        0x1
#define TIMER_CONT      0x2
#define TIMER_START     0x4
#define TIMER_STOP      0x8

int main(void)
{
    const unsigned int half_second = 50000000u;  /* 100 MHz timer clock */
    int led = 0;

    TIMER_CONTROL = TIMER_STOP;
    TIMER_PERIOD_LO = (short)(half_second & 0xFFFFu);
    TIMER_PERIOD_HI = (short)((half_second >> 16) & 0xFFFFu);
    TIMER_STATUS = 0;  /* clear TO */
    TIMER_CONTROL = TIMER_CONT | TIMER_START;

    while (1) {
        if ((TIMER_STATUS & TIMER_TO) != 0) {
            TIMER_STATUS = 0;  /* clear TO */
            led ^= 1;
            *LEDS = led;
        }
    }
    return 0;
}

Use the table to record the timer-driven blink. Keep the 10-second window unless your teacher asks for a longer test. In the evidence column, write what changed, for example off -> on -> off, then enter pass, fail, or uncertain.

Choose one validated example and make a small, observable change.

Examples:

- In hex_counter, change the display sequence so it counts only even hexadecimal values.
- In hex_counter, drive two HEX digits instead of only HEX0.
- In timer_blink, change the timer period so LEDR0 blinks faster or slower.
- In timer_blink, toggle a different LED bit.
- Optional button work: read JP1 bits 0 through 3 from NB0..NB3 and show them on LEDR0..LEDR3.

The logical NB0..NB3 buttons are validated through the JP1 data register bits 0 through 3. They are useful for a quick polling exercise, but they are not the FPGAcademy KEY3..KEY0 port.

Minimal C pattern:

volatile int *LEDS = (int *) 0xFF200000;
volatile int *JP1 = (int *) 0xFF200060;
volatile int *JP1_DIR = (int *) 0xFF200064;

*JP1_DIR = 0;
while (1) {
    *LEDS = (*JP1) & 0xF;   // NB0..NB3 -> LEDR0..LEDR3
}

The capstone must use NSW0..NSW9 and LEDR0..LEDR9 plus at least one validated extension peripheral from this lesson.